In the semiconductor manufacturing industry, the method for creating recipes for scanning electron microscopes (SEMs) and other metrology equipment has historically been a manual operation with human operator intervention. This has generally been the case in the production environment as well as in the evaluation and qualification of metrology equipment. The manual methods may require that the recipe developer collect various items of information related to the exposure of a mask level, then, after programming such information into the SEM or other metrology tool, visually and manually search on the patterned wafer to be measured, to manually locate the test feature. This is labor intensive and time consuming. After inputting the various data then manually locating the test feature to be measured, the recipe developer must then input additional information to allow the recipe generator to generate a useable recipe for carrying out various metrology measurements on fabricated test structures.
This operation sequence is required to be carried out at each of the multiple mask levels used in manufacturing a semiconductor device. Alternatively stated, for each semiconductor device or part, there are multiple metrology recipes that must be created, sometimes up to thirty (30) or more. While some waferless metrology recipe generation techniques are known, the known techniques lack the accuracy necessary for the pattern recognition capabilities of the metrology equipment being used and typical automatic recipes frequently result in the metrology tool failing to find the test feature and an error signal being generated. Because of these shortcomings, the typical method of locating a test structure remains loading a patterned wafer into the SEM or other metrology tool and visually searching within the exposure field to find the test structure. Only after the feature is visually located using manual techniques, the recipe editor software available in the metrology tool may be used to generate the recipe. The labor intensive and time consuming process of manually finding the test feature can be made more difficult depending on the mask layout, for example if chip sizes are small and the number of scribe lines is therefore increased.
It would therefore be advantageous to provide a method and system for metrology recipe generation that does not require the patterned wafer to be referenced at all, much less visually scanned. Some waferless metrology recipe generation techniques are known in the art, such as U.S. Pat. No. 6,886,153 B1 to Bevis, issued Apr. 26, 2005 and United States Patent Application Publication U.S. 2004/0030430 A1 to Matsuoka, filed Jun. 26, 2003. These and other conventional waterless metrology recipe generators include various shortcomings that preclude these teachings from providing a method to automatically generate a metrology recipe without referencing a wafer and which provides accuracy that positions the cursor or measurement focus of the metrology system within 10 microns of the test structure to be measured.
It would therefore be desirable to provide such an automatic metrology wafer generation method. It would be further desirable to provide a method and system that queries various available databases to also obtain the necessary information required to generate such a recipe.